科技與工程學院

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沿革

科技與工程學院(原名為科技學院)於87學年度成立,其目標除致力於科技與工程教育師資培育外,亦積極培育與科技產業有關之工程及管理專業人才。學院成立之初在原有之工業教育學系、工業科技教育學系、圖文傳播學系等三系下,自91學年度增設「機電科技研究所」,該所於93學年度起設立學士班並更名為「機電科技學系」。本學院於93學年度亦增設「應用電子科技研究所」,並於96學年度合併工教系電機電子組成立「應用電子科技學系」。此外,「工業科技教育學系」於98學年度更名為「科技應用與人力資源發展學系」朝向培育科技產業之人力資源專才。之後,本院為配合本校轉型之規劃,增加學生於科技與工程產業職場的競爭,本院之「機電科技學系」與「應用電子科技學系」逐漸朝工程技術發展,兩系並於103學年度起分別更名為「機電工程學系」及「電機工程學系」。同年,本學院名稱亦由原「科技學院」更名為「科技與工程學院」。至此,本院發展之重點涵蓋教育(技職教育/科技教育/工程教育)、科技及工程等三大領域,並定位為以技術為本位之應用型學院。

107學年度,為配合本校轉型規劃,「光電科技研究所」由原隸屬於理學院改為隸屬本(科技與工程)學院,另增設2學程,分別為「車輛與能源工程學士學位學程」及「光電工程學士學位學程」。

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    A miniature 38-48 GHz MMIC sub-harmonic transmitter with post-distortion linearization
    (2007-06-08) Jeng-Han Tsai; Tian-Wei Huang
    This paper presents a miniature 38-48 GHz sub-harmonic transmitter with post-distortion linearization using a 0.15-mum GaAs HEMT process. The transmitter, which integrates a sub-harmonic mixer, a band-pass driver amplifier, and a linearizer, has a compact chip size of 2.5 mm2 with conversion gain of 7 plusmn 1.5 dB from 38 to 48 GHz. With the features of the sub-harmonic mixer and band-pass driver amplifier, the 2fLO leakage rejection of the transmitter is 47 dB. For the linearity of the transmitter, a post-distortion linearizer is added. After linearization, the output spectrum re-growth can be suppressed by 8 dB at 40 GHz. To keep ACPR below -35 dBc, the output power has been increased from -2 to 1 dBm, which means the linear output power has been doubled after linearization.
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    A 24-GHz 3.8-dB NF Low-Noise Amplifier with Built-In Linearizer
    (2010-12-10) Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei Huang
    A K-band low-noise amplifier with built-in linearizer using 0.18-μm CMOS technology is presented in this paper. To achieve good linearity at high frequency, a distributed derivative superposition linearization technique is used. The measured results show that the improvement of IIP3 and IM3 are 5.3 dB and 10.6 dB at 24 GHz, respectively. The proposed LNA has a noise figure of 3.8 dB and a peak gain of 13.7 dB while consuming 18 mW dc power. To the best of our knowledge, this is the first LNA with a built-in linearizer above 20 GHz in CMOS.
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    A 60-GHz CMOS power amplifier with built-in pre-distortion linearizer
    (Institute of Electrical and Electronics Engineers (IEEE), 2011-12-01) Jeng-Han Tsai; Chung-Han Wu; Hong-Yuan Yang; Tian-Wei Huang
    A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power ampli- fier (PA) achieves a of 10.72 dBm and of 7.3 dBm from 1.2 V supply. After linearization, the has been doubled from 7.3 to 10.2 dBm and the operating PAE at consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.