科技與工程學院
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沿革
科技與工程學院（原名為科技學院）於87學年度成立，其目標除致力於科技與工程教育師資培育外，亦積極培育與科技產業有關之工程及管理專業人才。學院成立之初在原有之工業教育學系、工業科技教育學系、圖文傳播學系等三系下，自91學年度增設「機電科技研究所」，該所於93學年度起設立學士班並更名為「機電科技學系」。本學院於93學年度亦增設「應用電子科技研究所」，並於96學年度合併工教系電機電子組成立「應用電子科技學系」。此外，「工業科技教育學系」於98學年度更名為「科技應用與人力資源發展學系」朝向培育科技產業之人力資源專才。之後，本院為配合本校轉型之規劃，增加學生於科技與工程產業職場的競爭，本院之「機電科技學系」與「應用電子科技學系」逐漸朝工程技術發展，兩系並於103學年度起分別更名為「機電工程學系」及「電機工程學系」。同年，本學院名稱亦由原「科技學院」更名為「科技與工程學院」。至此，本院發展之重點涵蓋教育（技職教育/科技教育/工程教育）、科技及工程等三大領域，並定位為以技術為本位之應用型學院。
107學年度，為配合本校轉型規劃，「光電科技研究所」由原隸屬於理學院改為隸屬本（科技與工程）學院，另增設2學程，分別為「車輛與能源工程學士學位學程」及「光電工程學士學位學程」。
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Item A V-band VCO using fT-doubling technique in 0.18-μm CMOS(2011-12-08) Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; Huei WangA low supply voltage V-band voltage-controlled oscillator (VCO) using fT-doubling technique is presented in this paper. The proposed VCO is fabricated in 0.18-μm CMOS technology. The proposed VCO adopts the fT-doubling technique to eliminate the gate-to-source capacitance of cross-coupled pair of VCO. The oscillation frequency of VCO can be increased due to the parasitic capacitance is eliminated. The measured results show that the proposed VCO have tuning range of 0.74 GHz from 58.09-to-58.83 GHz. The proposed VCO consumes 4 mW dc power from 1.2 V supply voltage.Item Admittance-Transforming Injection-Locked Frequency Divider and Low-Supply-Voltage Current Mode Logic Divider(2010-12-10) Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei HuangA injection-locked frequency divider (ILFD) with a 0.8-V current mode logic (CML) frequency divider are presented in this paper. These two frequency dividers are fabricated and integrated in 0.13-μm CMOS technology. The proposed ILFD adopts the admittance-transforming to widen the locking range. To achieve low-supply-voltage in CML frequency divider, the transconductance stage of CML divider is replaced by the inductance. Under 0 dBm injected power, the measured results show that the proposed ILFD have 22.8 % bandwidth from 40.5-to-50.9 GHz. Furthermore, the divider-by-four frequency divider composed of an ILFD and CML divider are measured with locking range from 42 to 45 GHz. The ILFD and CML divider consume 3.6 mW and 8 mW dc power from 0.6 V and 0.8 V supply voltage, respectively.Item An ultra low-power 24 GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process(2011-12-08) Yu-Hsuan Lin; Jeng-Han Tsai; Yen-Hung Kuo; Tian-Wei HuangA 24 GHz 29.8 mW Phase-lock-loop using 0.18 μm CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by -122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm2 without off-chip loop filter.Item A 24-GHz 3.8-dB NF Low-Noise Amplifier with Built-In Linearizer(2010-12-10) Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei HuangA K-band low-noise amplifier with built-in linearizer using 0.18-μm CMOS technology is presented in this paper. To achieve good linearity at high frequency, a distributed derivative superposition linearization technique is used. The measured results show that the improvement of IIP3 and IM3 are 5.3 dB and 10.6 dB at 24 GHz, respectively. The proposed LNA has a noise figure of 3.8 dB and a peak gain of 13.7 dB while consuming 18 mW dc power. To the best of our knowledge, this is the first LNA with a built-in linearizer above 20 GHz in CMOS.Item Design and analysis of a 77.3% locking-range divide-by-4 frequency divider(IEEE Microwave Theory and Techniques Society, 2011-10-01) Yen-Hung Kuo; Jeng-Han Tsai; Hong-Yeh Chang; Tian-Wei HuangA cascoded frequency divider (FD) with division number of 4 and ultra-wide locking range is presented in this paper. The proposed FD consists of a divide-by-2 (D2) injection-locked frequency divider (ILFD) core and a D2 source-injection current mode logic (SICML) divider. After the cascoded integration of ILFD and SICML, the removal of transconductance and buffer stages can lower the dc power consumption and widen the locking range. The proposed FD is implemented in 0.13-μm CMOS technology and has a 77.3% frequency locking range from 13.5 to 30.5 GHz at injection power of 0 dBm while consuming 7.3-mW dc power. Compared to the previously reported ILFDs, the proposed circuit achieves the widest locking range without employing extra tuning mechanism.