使用巢狀雜訊耦合架構之三階前饋式雜訊整形連續漸進式類比數位轉換器

Abstract

隨物聯網技術快速演進，感測器在環境監測與工業自動化等應用中扮演關鍵角色。高解析度類比數位轉換器(ADC)在這些應用中扮演了關鍵的角色。為滿足感測系統對高解析度與低功率消耗的需求，採用雜訊整形連續漸進式類比數位轉換器(NS-SAR)相較於傳統以快閃式暫存器(Flash Register)為基礎的設計，不僅能降低功耗，還能維持高解析度，使其成為更適合低功耗設計需求的解決方案。本論文以實現低功耗之高解析度類比數位轉換器為目標，提出一個三階雜訊整形連續漸進式類比數位轉換器(NS-SAR)，使用雜訊耦合技術(Noise-Couple)並結合分散式前饋串聯積分器(CIFF)與巢狀式誤差回授(Error Feedback)架構，以實現高效能的雜訊整形。第一級採用主動積分器，增強雜訊抑制能力；第二、三級則利用雜訊耦合技術，利用乒乓延遲（Ping-pong delay）單元與單位增益緩衝器輔助傳遞量化誤差並回授至主迴路中，以實現三階雜訊整形。此作法可省去使用多組主動式積分器，同時達成高階雜訊整形，可有效節省功耗與電路面積，並簡化電路複雜度。此晶片使用台積電0.18um CMOS Mixed Signal RF General製程實現，在佈局後模擬中，於8MHz取樣頻率，訊號頻寬125kHz下實現了84.82dB的訊號雜訊失真比。並在供應電壓1.4V下，整體功率消耗為224.5uW。

With the rapid growth of IoT technologies, smart sensors have become essential in applications like environmental monitoring and industrial automation. High-resolution ADCs are critical in these systems. To meet the needs for high resolution and low power, noise-shaping SAR ADCs offer better power efficiency than traditional Flash Register-based designs while maintaining resolution, making them ideal for low-power applications.This work proposes a third-order NS-SAR ADC targeting low-power, high-resolution performance. The design integrates noise-coupling techniques with a cascaded integrator feedforward (CIFF) and nested error feedback architecture to achieve efficient noise shaping. An active integrator is employed in the first stage to enhance low-frequency noise suppression and linearity, while the second and third stages use a noise-coupling structure with ping-pong delay cells and unity-gain buffers to transfer quantization errors back to the main loop.The chip is implemented using TSMC 180nm CMOS Mixed Signal RF General process. Post-layout simulation shows an SNDR of 84.82 dB at an 8 MHz sampling rate and 125 kHz bandwidth, with total power consumption of 224.5 μW under a 1.4V supply.