應用於5G FR2與Wi-Fi 7之功率放大器設計

Abstract

本論文依據操作頻段分為兩個部分。第一部分介紹一款應用於5G通訊之Ka頻段功率放大器，採用65奈米金屬氧化物半導體場效電晶體（MOSFET）製程進行模擬與實現；第二部分則探討一款針對Wi-Fi 7應用設計之功率放大器，採用28奈米MOSFET製程進行模擬設計。在第一部分中，提出一款基於65奈米 CMOS製程，應用於5G FR2 上行鏈段之功率放大器，採用二級串接架構與中和電容（Neutralization）技術，以提升差動增益與系統穩定性；另引入振幅線性化電路（Amplitude Linearizer），擴展線性輸出範圍。量測結果顯示，在27 GHz下可達到40.4 %之功率附加效率（PAEpeak）與14.1 dBm的最大輸出功率（Psat），同時可將1 dB增益壓縮點的輸出功率（OP1dB）提升2.9 dB。第二部分中，模擬一款基於28 奈米CMOS製程、對應IEEE 802.11be頻段之Wi-Fi 7功率放大器，採用單級疊接（Cascode）架構以提升輸出功率，並透過中和電容強化穩定性。另設計線性化電路以修正電晶體非線性行為，進一步擴大線性輸出區域。模擬結果顯示可達到43.4 %功率附加效率與29.2 dBm最大輸出功率；於相位-振幅線性化器啟動狀態下，OP1dB最大可提升7.4 dB (20.1 dBm提升至27.5 dBm)。關鍵字：互補式金屬氧化物半導體、功率放大器、失真、補償電路、Wi-Fi 7、Ka頻段、線性化。

This thesis is divided into two parts based on operating frequency. The first part presents a Ka-band power amplifier (PA) for 5G communication, designed and im-plemented using a 65-nm MOSFET process.The second part explores a Wi-Fi 7 PA designed with a 28-nm MOSFET process.In the first part, a two-stage cascade d Ka-band PA with neutralization is pro-posed to enhance differential gain and stability. An amplitude linearizer is also in-troduced to extend the linear output range. Measurements show a peak power-added efficiency (PAEpeak) of 40.4 % and a maximμm output power (Psat) of 14.1 dBm at 27 GHz, with a 2.9 dB improvement in OP1dB.In the second part, a Wi-Fi 7 PA operating in the IEEE 802.11be frequency band is simulated using a 28-nm MOSFET process. A single-stage cascode architecture enhances output power, while neutralization improves stability. A linearization circuit further corrects transistor nonlinearity, expanding the linear output range. The simu-lation results demonstrate a PAEpeak of 43.4 % and Psat of 29.2 dBm, with the OP1dB improved by 7.4 dB under combined phase and amplitude linearization—from 20.1 dBm to 27.5 dBm. Keywords : CMOS, power amplifier, distortion, compensated network, Wi-Fi 7, Ka-Band, linearization.