應用於N型電晶體與射頻電路之靜電放電防護設計

Abstract

隨著製程發展，積體電路越發脆弱，而靜電荷仍存在於環境，故靜電放電為積體電路可靠度的重要議題。為了使各電路在最小的影響下有足夠的靜電放電耐受度，須考量各種因素。部分應用因成本、性能或是製程上的限制，只能採用全N型電晶體設計，因此本論文提出了全N型電晶體之靜電放電防護設計，而部分高速或射頻電路也因性能考量使用全N型電晶體設計，在此類應用下還須考量寄生電容以避免影響高頻特性，此外，面積也是一大考量，以符合成本上的要求。本論文提出四種全NMOS之電源間靜電放電箝制電路與一種應用於射頻電路之主動式靜電放電防護設計，前者採用全NMOS設計並可節省12-14%的面積，且於實驗結果中展現出比傳統電路更高的靜電放電耐受度、相似的箝制電壓與漏電流，而與過往常見的全NMOS防護設計相比也有足夠低的觸發電壓以應用於先進製程；後者於訊號端上使用二極體作為放電元件，但此作法在10GHz以上頻段仍有較高的插入損耗，而使用電感會使面積過大，故採用一放大器提升二極體在13-17GHz下的高頻性能，且不影響其防護能力，此提出設計相比其他文獻可有更高的效用，於未來工作中也提出了採全NMOS的主動式靜電放電防護設計。

With the development of process technology, integrated circuits become more fragile, while electrostatic charges persist in the environment. Thus, electrostatic discharge (ESD) has been a crucial issue for the reliability of integrated circuits. In order to ensure sufficient ESD robustness for various circuits and minimize the impact on the internal circuits, various factors must be considered. Due to limitations on cost, performance, or process, these ICs consist solely of N-type transistors. Therefore, all N-type transistor ESD protection designs are proposed to meet these applications in this thesis. However, high-speed or radio-frequency circuits, which must also consider parasitic capacitance to avoid affecting the high-frequency performance, often employ an all N-type transistor design due to performance considerations. Additionally, area considerations are also critical to meet the requirement of cost.This thesis proposes four all-NMOS power-rail ESD clamp circuits and one active ESD protection design for radio-frequency circuits. The former adopts an all-NMOS design and can save 12-14% of the area. In the experimental results, the proposed circuits exhibit higher ESD robustness, similar clamping voltage, and comparable leakage compared to the traditional circuit. The proposed circuits also have a sufficientlylow trigger voltage, making them more appropriate for advanced process technology compared to other all-NMOS ESD protection circuits. The latter uses diodes as the ESD protection device at the signal terminal, but this method still causes a high insertion loss for frequencies above 10GHz. Because using inductors will occupy a large area, an amplifier is proposed and utilized to enhance the high-frequency performance of the diodes at 13-17GHz. This amplifier has not impact on the ESD protection ability. Therefore, this proposed design for radio-frequency circuits can achieve sufficient ESD robustness and higher cost-efficiency compared to other literature. In future work, an active all-NMOS ESD protection design is also proposed to address all N-type transistor and parasitic capacitance issues.