含浮點運算之管線化MIPS CPU設計與FPGA實作

Abstract

數位電路的產物中，舉凡電腦、手機、家電產品等等，其中央處理器（CPU）扮演著非常重要的角色。隨著產品的複雜度和功能的多寡，CPU的處理速度也一直在提升，自管線式（Pipeline）架構被提出來以後，已成為高速處理器的主流。 本研究主要目的在於以HDL（Hardware Description Language）硬體描述語言，設計一顆具有五階層的Pipelined MIPS CPU，並針對管線中會發生的三大危障(hazard)：結構危障(structure hazard)、資料危障(data hazard)、控制危障(control hazard)，設計解決的機制，以增加CPU的效能。 設計結果經由ModelSim完成電路模擬後，下載至Xilinx Virtex XCV800 FPGA(Field Programmable Gate Array)驗證成功，完成整體設計架構，並加入周邊介面I/O電路設計和周邊顯示電路的實體連接，完成FPGA平台設計架構。最後，利用所設計的指令集撰寫相關程式，來驗證整個Pipelined MIPS CPU的運作。 本研究結果已成功完成一顆五階層的Pipelined MIPS CPU（包含浮點數指令），並解決三大危障等問題，總共實作了21道固定點指令、4道浮點指令。Central processing unit in the now times plays a key essential role amid various logic circuit products. Due to demanding increasing complexity and enhanced function, CPU processing speed is requested to rapidly accelerate in all the field with CPU inside such as computer, handset, home appliance etc. The main purpose of this reserach is to design a five stages pipelined MIPS CPU with hardware description language to resolve structure, data and control three major hazards in pipeline system, design resolution mechanism and increase CPU efficiency. The research is verified by that the simulated circuit and downloaded to Xilinx Virtex XCV800 FPGA. After downloading, then connect the relating circuit designing and the physical circuit to display on the 20×20 LCD.When the stage is ok, the whole FPGA structure is down. Finally I test the Pipelined MIPS CPU by the relate command. The research is including twenty-one fixed instructions and four floating instructions.