以FPGA為硬體架構基礎之數位全像重建系統

Abstract

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A novel hardware architecture for the reconstruction of digital holograms with autofocusing is presented in this dissertation. A fast autofocusing algorithm operating on a smaller local block locating at the center of the source digital holograms is proposed. By exploiting global information contained in the local block, accurate focus distance can be computed with less computational complexities. Interval search is also adopted to further accelerate the process. The circuits for the fast autofocusing algorithm and subsequent reconstruction operations are effectively integrated in the proposed architecture. Two FFT cores are shared by the operations for parallel computations with low area costs. The architecture is implemented by field programmable gate array (FPGA), and is used as a hardware accelerator in a network on chip (NOC) system for performance evaluation. Experimental results demonstrate that the proposed circuit exhibits the advantages of high speed computation, low power dissipation and accurate focus distance search and hologram reconstruction for 3D rendering applications.