教師著作
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Item A 0.6 V low-power 3.5 GHz CMOS low noise amplifier for WiMAX applications(Wiley-Blackwell, 2012-01-01) Jeng-Han Tsai; Yi-Jhang Lin; Hao-Chun YuIn this letter, a low-voltage and low-power 3.5-GHz low noise amplifier (LNA) is designed and fabricated using TSMC 0.18-lm MS/RF complementary metal-oxide-semiconductor field effect transistor (CMOS) technology. The complementary current-reused topology is utilized to achieve low dc power consumption while maintaining reasonable gain performance. Consuming 1.38 mW dc power from 0.6 V supply, the LNA achieves a small signal gain of 16.09 dB and a noise figure of 4.702 dB at 3.5 GHz. Compared with previously reported LNA, the MMIC has excellent FOM performance. VC 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:145–147, 2012; View this article online at wileyonlinelibrary.comItem A 0.8V SOP-Based Cascade Multibit Delta-Sigma Modulator for Wideband Applications(2008-12-03) Chien-Hung Kuo; Kuan-Yi Lee; Shuo-Chau ChenIn this paper, a 0.8 V switched-opamp (SOP)-based 2-2 cascade delta-sigma modulator for wideband applications is presented. The first stage uses low-distortion topology to release the requirement of SOP due to only the quantization noise in integrator path. The second stage employs a CIFB structure without the use of summer in front of the quantizer to decrease the power consumption. Double sampling technique combined with the SOP with two output stages is used to promote the clock efficiency. The proposed fourth-order DeltaSigma modulator with CIFFCIFB structure has been implemented in a 0.13 mum CMOS 1P8M technology. The core area excluding PADs is 1.66times1.62 mm2. The peak signal-to-noise plus distortion ratio (SNDR) and dynamic range (DR) of the presented modulator within a 1.1 MHz of bandwidth are 77.9 dB and 85 dB, respectively, under a 20 MHz of clock rate. The power dissipation of the presented DeltaSigma modulator is 15.7 mW at a 0.8 V of supply voltage.Item A 0.8V SOP-Based Wideband Fourth-Order Cascade Delta-Sigma Modulator(2007-08-01) Chien-Hung Kuo; Shuo-Chau ChengItem 0.9V以下低電壓應用於寬頻之低通三角積分調變器之研製(行政院國家科學委員會, 2007-07-31) 郭建宏隨著可攜式電子產品市場的快速成長，以及人們對於產品輕薄短小和 電池的長時效性要求，低電壓、低功率積體電路技術發展有愈來愈急迫的 需要。然而，電源電壓的下降，雖可有效地節省數位電路的消耗功率，但 卻反而增加類比電路設計的困難。因此，類比電路若要操作在低電壓，又 要維持和高電壓相同的性能，對設計者來說是一項很大的挑戰。 三角積分調變器這項技術非常適合用來實現高解析度、高準確度的類 比數位轉換器，這在通信上有很相當多的應用。在本計劃的研究中，是要 設計一個可操作在寬頻、0.9伏特以下的開關運算放大器，進而合成一個低 電壓的二階積分器，及一個新的低電壓多位元寬頻的低通三角積分調變 器，藉以提升類比數位轉換器在低電壓應用層面，以達到SoC的目標。研究 步驟包含以下四個步驟： (1) 第一部份提出符合需求的高階多位元類比數位轉換器架構，並在回授 路徑不匹配的考量下，利用MATLAB做電路係數的最佳化，求出較佳 的電路架構。 (2) 第二部份在元件的非理想特性下，以CMOS技術設計出符合寬頻應用範 圍的開關式運算放大器。 (3) 第三部份，以電路特殊技巧設計出僅用一個開關運算放大器合成一個 低電壓二階多位元之積分器，以減少晶片所需面積及消耗功率。再利 用此二階積分器，結合多位元量化器電路，合成一個低電壓高階多位 元之低通寬頻三角積分調變器，以期能有效提高類比數位轉換時的解 析度，符合低電壓、高性能應用上的需求。Item 0.9V低電壓多位元高解析度低通三角積分調變器之研製(行政院國家科學委員會, 2006-07-31) 郭建宏隨著可攜式電子產品市場的快速成長，以及人們對於產品輕薄短小和 電池的長時效性要求，低電壓、低功率積體電路技術發展有愈來愈急迫的 需要。然而，電源電壓的下降，雖可有效地節省數位電路的消耗功率，但 卻反而增加類比電路設計的困難。因此，類比電路若要操作在低電壓，又 要維持和高電壓相同的性能，對設計者來說是一項很大的挑戰。 三角積分調變器這項技術非常適合用來實現高解析度、高準確度、及 窄頻要求的類比數位轉換器，這在音頻及通信上有很相當多的應用。在本 計劃的研究中，是要設計一個開關運算放大器合成一個0.9伏特的二階積分 器，及一個新的低電壓多位元量化器的架構；並利用此積分器結合低電壓 多位元量化器合成一個二階多位元的低通三角積分調變器，藉以提升類比 數位轉換器在低電壓應用的解析度，以達到SOC的目標。研究步驟包含以 下四個步驟： (1) 第一部份提出符合需求的二階多位元類比數位轉換器架構，並在回授 路徑不匹配的考量下，利用MATLAB做電路係數的最佳化，求出較佳 的電路架構。 (2) 第二部份在元件的非理想特性下，設計出符合應用範圍的開關式運算 放大器規格。並以CMOS技術設計出符合需求的開關式運算放大器。 (3) 第三部份，設計出低電壓多位元之量化器電路，以符合三角積分調變 器的應用。 (4) 第四部份，以電路特殊技巧設計出僅用一個開關運算放大器合成一個 低電壓二階多位元之積分器，以減少晶片所需面積及消耗功率。再利用此二階積分器，結合多位元量化器電路，合成一個低電壓二階多位 元之低通三角積分調變器，以期能有效提高類比數位轉換時的解析 度，符合低電壓、高性能應用上的需求。Item A 1-V 10.7MHz Fourth-Order Bandpass ΔΣ Modulators Using Two Switched Opamps(Institute of Electrical and Electronics Engineers�(IEEE), 2004-11-01) Chien-Hung Kuo; Shen-Iuan LiuA 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25- m 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is 65 dBc below the desired signal.Item A 1.5-mW, 23.6% frequency locking range,24-GHz injection-locked frequency divider(2010-09-30) Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei HuangA K-band low-power and wideband injection-locked frequency divider (ILFD) using 0.18-μm CMOS technology is presented in this paper. To achieve the wide-locking-range and low-power consumption, the inductive peaking and current-reused techniques are adopted. The measurement results show that the proposed ILFD has a locking range of 5.5 GHz (23.6%), from 20.5 to 26 GHz, at the incident power of 0 dBm, with a very low power consumption of 1.5 mW. Among 180 nm and 130 nm CMOS frequency dividers, the proposed ILFD achieves wide locking range with the lowest dc power and RF injected power at K-band.Item A 1.7-mW, 14.4% Frequency Tuning,24GHz VCO with Current-Reused Structure Using 0.18-μm CMOS Technology(2009-06-01) Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei HuangItem A 1V 82dB Multibit Delta-Sigma Modulator(2006-08-11) Chien-Hung Kuo; Kang-Shuo Chang; Jing-Shan JianThis paper proposes a double-sampling multibit delta sigma modulator with a single switched-opamp at a 1V of supply voltage. Two new digital-to-analog converter feedbacks for the low voltage modulator are developed to overcome the driving problem of the switches and minimize the number of capacitors used in the feedbacks of the modulator. The proposed modulator has been implemented with a second-order 3-bit modulator in a 0.18.mu.m 1P6M CMOS process. The measured signal-to-noise ratio and dynamic range of the modulator in a 24kHz of bandwidth are 80dB and 82dB, respectively, under a 2.5MHz of clock rate. The power consumption of the modulator is 1.8mW at 1V of supply voltage.Item 2-Dimenional Localization Based on Tilt Photographing of a Single CCD Camera(2009-02-12) Ming-Yu Cheng; Chen-Chien Hsu; Pei-Jun LeeThis paper provides an image-based localization method based on tilt photographing of a single CCD camera. Image captured by the CCD camera is pre-processing to locate the target object in the picture in terms of pixel count deviation from the CCD camera. By using an established formula based on relationship between tilt angle of the CCD camera and distance, coordinate of the target object can be calculated. Experiment results have demonstrated that the feasibility of the proposed approach with satisfactory accuracy in determining the position of the target object.Item A 20 to 24 GHz +16.8-dBm fully integrated power amplifier using 0.18-痠 CMOS process(IEEE Microwave Theory and Techniques Society, 2009-01-01) Yung-Nien Jen; Jeng-Han Tsai; Chung-Te Peng; Tian-Wei HuangA 20-24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 mum standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm2, which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 mm2, which is the smallest one compared to all reported paper.Item 24 GHz CMOS 收發器線性化技術(行政院國家科學委員會, 2009-07-31) 蔡政翰本計畫將開發應用於下一代寬頻高速的無線通信系統的24GHz 高線性度收發器積 體電路，實現的方法將使用互補式金氧半導體之積體電路技術。計畫目標是研究利用矽 基製程技術，開發24GHz 收發器積體電路，包括功率放大器、低雜訊放大器、與混頻 器等。並且爲了滿足現今高速無線數位通信系統嚴格的線性度要求，本計畫針對發射器 中的關鍵元件，作線性度的分析，並且發展線性化技術，達到在有限的電能消耗下，設 計一24GHz CMOS 高線性度收發器的目標。Item A 24-GHz 3.8-dB NF Low-Noise Amplifier with Built-In Linearizer(2010-12-10) Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei HuangA K-band low-noise amplifier with built-in linearizer using 0.18-μm CMOS technology is presented in this paper. To achieve good linearity at high frequency, a distributed derivative superposition linearization technique is used. The measured results show that the improvement of IIP3 and IM3 are 5.3 dB and 10.6 dB at 24 GHz, respectively. The proposed LNA has a noise figure of 3.8 dB and a peak gain of 13.7 dB while consuming 18 mW dc power. To the best of our knowledge, this is the first LNA with a built-in linearizer above 20 GHz in CMOS.Item A 25-55 GHz CMOS sub-harmonic direct-conversion mixer for BPSK demodulator(2008-12-20) Jeng-Han Tsai; Chieh-Cheng WangIn this paper, a sub-harmonic direct-conversion Gilbert-cell mixer using 0.13-frac14m CMOS technology for BPSK demodulator is presented. For sub-harmonically pumping, a four-way quadrature divider using 90deg coupler and 180deg balun is implemented in the CMOS process [6]. For wide bandwidth, distributed transconductance stage design and high impedance compensation line are incorporated into the sub-harmonic Gilbert-cell design. The presented sub-harmonic Gilbert-cell mixer achieves an excellent conversion gain flatness of-5.5 plusmn1.5 dB from 25 to 55 GHz. Finally, the direct-conversion sub-harmonic Gilbert-cell mixer is used as a BPSK demodulator and features good demodulation quality.Item A 25-75-GHz broadband Gilbert-cell mixer using 90-nm CMOS technology(IEEE Microwave Theory and Techniques Society, 2007-04-01) Jeng-Han Tsai; Pei-Si Wu; Chin-Shen Lin; Tian-Wei Huang; John G.J. Chern; Wen-Chu Huang; Huei WangA compact and broadband 25-75-GHz fully integrated double-balance Gilbert-cell mixer using 90-nm standard mixed-signal/radio frequency (RF) CMOS technology is presented in this letter. A broadband matching network, LC ladder, for Gilbert-cell mixer transconductance stage design is introduced to achieve the flatness of conversion gain and good RF port impedance match over broad bandwidth. This Gilbert-cell mixer exhibits 3plusmn2dB measured conversion gain (to 50-Omega load) from 25 to 75GHz with a compact chip size of 0.30mm2. The OP1 dB of the mixer is 1dBm and -4dBm at 40 and 60GHz, respectively. To the best of our knowledge, this monolithic microwave integrated circuit is the highest frequency CMOS Gilbert-cell mixer to dateItem A 3.5-4.5-GHz ultra-compact 0.25mm square reflection-type 360 degree phase shifter(2011-06-07) Wei-Tsung Li; Jeng-Han Tsai; Min Huang; Tian-Wei HuangAn ultra-compact reflection-type phase shifter (RTPS) with full 360° continuous phase shift and low insertion loss using standard 0.18-μm CMOS technology is demonstrated in this paper. Dual active reflection load using active inductor is utilized in the proposed reflection-type load to cover 360 ° phase tuning through only one quadrature hybrid, which has the advantages of compact chip size, low insertion loss, and low loss variation. Measurements show better than 15 dB input/output return loss, signal losses of 6.4dB±1.5dB, less than 2.4dB±0.6 dB loss variation, and a 360 ° continuously tunable range across 3.5~4.5 GHz with 3.4mW dc power consumption. To the best of our knowledge, the proposed phase shifter has the smallest die size, 0.25 mm2, among all reported 360° C-band CMOS RTPS, which is important for a large phase array system.Item A 30-100-GHz wideband sub-harmonic active mixer in 90-nm CMOS technology(IEEE Microwave Theory and Techniques Society, 2008-08-01) Jeng-Han Tsai; Hong-Yuan Yang; Tian-Wei Huang; Huei WangThis letter presents a 30-100 GHz wideband and compact fully integrated sub-harmonic Gilbert-cell mixer using 90 nm standard CMOS technology. The sub-harmonic pumped scheme with advantages of high port isolation and low local oscillation frequency operation is selected in millimeter-wave mixer design. A distributed transconductance stage and a high impedance compensation line are introduced to achieve the flatness of conversion gain over broad bandwidth. The CMOS sub-harmonic Gilbert-cell mixer exhibits -1.5 plusmn 1.5 dB measured conversion gain from 30 to 100 GHz with a compact chip size of 0.35 mm2. The OP1 dB of the mixer is -10.4 dBm and -9.6 dBm at 77 and 94 GHz, respectively. To the best of our knowledge, the monolithic microwave integrated circuit is the first CMOS Gilbert-cell mixer operating up to 100 GHz.Item A 30-60GHz CMOS sub-harmonic IQ de/modulator for high data-rate communication system applications(2009-01-22) Wei-Heng Lin; Wei-Lun Chang; Jeng-Han Tsai; Tian-Wei HuangA 30-60 GHz sub-harmonic IQ de/modulator using TSMC CMOS 0.13-mum process is presented in this paper. The IQ de/modulator consists of two FET resistive mixers, a 90deg coupler, and a Wilkinson power divider. The resistive mixer could simultaneously used as a up-converted or a down-converted mixer. Therefore, the measurement of the FET resistive mixer based modulator or demodulator will be done. The die size is 0.78 mm times 0.58 mm. Both IQ demodulator and modulator feature the conversion loss of -16plusmn1 dB and good demodulation and modulation capacity.Item A 30-GHz Low-Phase-Noise 0.35-μm CMOS Push-Push Oscillator Using Micromachined Inductors(2006-06-16) To-Po Wang; Ren-Chieh Liu; Hong-Yeh Chang; Jeng-Han Tsai; Liang-Hung Lu; Huei WangA low-phase-noise 0.35-mum CMOS push-push oscillator utilizing micromachined inductors is presented in this paper. With the micromachined high-Q inductors, the oscillator achieves an oscillating frequency of 30.9 GHz while exhibiting an output power of -4 dBm with a low phase noise of -102.3 dBc/Hz at 1-MHz offset and the figure of merit (FoM) of -171.4 dBc/Hz. The fundamental rejection is 30 dB. This oscillator achieves low phase noise, good FOM, high output power, and also demonstrates the highest operating frequency among previously published Si-based and GaAs-based VCOs using micromachined structuresItem A 35-45-GHz CMOS Amplifier with Defected Ground Structure Matching Networks(2009-04-22) Jeng-Han Tsai; Chieh-Cheng Wang