教師著作

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    A 38-46-GHz MMIC Doherty power amplifier using post-distortion linearization
    (IEEE Microwave Theory and Techniques Society, 2007-05-01) Jeng-Han Tsai; Tian-Wei Huang
    This letter describes the first demonstration of a fully integrated Doherty power amplifier (PA) monolithic microwave integrated circuit (MMIC) with post-distortion linearization at millimeter-wave (MMW) frequency band. The Doherty amplifier MMIC, using a 0.15-mum GaAs HEMT process, achieves a small signal gain of 7dB from 38 to 46GHz with a compact chip size of 2mm2. The saturation output power of the Doherty amplifier is 21.8dBm. The similar topology between the Doherty amplifier and post-distortion linearization makes it possible to improve efficiency and linearity simultaneously in MMW PA designs. After gate bias optimization of the main and peaking amplifier, the drain efficiency improved 6% at 6-dB output back-off and the inter-modulation distortion (IMD) of quasi Doherty amplifier can be improved 18dB at 42GHz compared with the balanced amplifier operation
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    A 30-100-GHz wideband sub-harmonic active mixer in 90-nm CMOS technology
    (IEEE Microwave Theory and Techniques Society, 2008-08-01) Jeng-Han Tsai; Hong-Yuan Yang; Tian-Wei Huang; Huei Wang
    This letter presents a 30-100 GHz wideband and compact fully integrated sub-harmonic Gilbert-cell mixer using 90 nm standard CMOS technology. The sub-harmonic pumped scheme with advantages of high port isolation and low local oscillation frequency operation is selected in millimeter-wave mixer design. A distributed transconductance stage and a high impedance compensation line are introduced to achieve the flatness of conversion gain over broad bandwidth. The CMOS sub-harmonic Gilbert-cell mixer exhibits -1.5 plusmn 1.5 dB measured conversion gain from 30 to 100 GHz with a compact chip size of 0.35 mm2. The OP1 dB of the mixer is -10.4 dBm and -9.6 dBm at 77 and 94 GHz, respectively. To the best of our knowledge, the monolithic microwave integrated circuit is the first CMOS Gilbert-cell mixer operating up to 100 GHz.
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    Design and analysis of a 77.3% locking-range divide-by-4 frequency divider
    (IEEE Microwave Theory and Techniques Society, 2011-10-01) Yen-Hung Kuo; Jeng-Han Tsai; Hong-Yeh Chang; Tian-Wei Huang
    A cascoded frequency divider (FD) with division number of 4 and ultra-wide locking range is presented in this paper. The proposed FD consists of a divide-by-2 (D2) injection-locked frequency divider (ILFD) core and a D2 source-injection current mode logic (SICML) divider. After the cascoded integration of ILFD and SICML, the removal of transconductance and buffer stages can lower the dc power consumption and widen the locking range. The proposed FD is implemented in 0.13-μm CMOS technology and has a 77.3% frequency locking range from 13.5 to 30.5 GHz at injection power of 0 dBm while consuming 7.3-mW dc power. Compared to the previously reported ILFDs, the proposed circuit achieves the widest locking range without employing extra tuning mechanism.