教師著作
Permanent URI for this collectionhttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/31268
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Item A V-band VCO using fT-doubling technique in 0.18-μm CMOS(2011-12-08) Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; Huei WangA low supply voltage V-band voltage-controlled oscillator (VCO) using fT-doubling technique is presented in this paper. The proposed VCO is fabricated in 0.18-μm CMOS technology. The proposed VCO adopts the fT-doubling technique to eliminate the gate-to-source capacitance of cross-coupled pair of VCO. The oscillation frequency of VCO can be increased due to the parasitic capacitance is eliminated. The measured results show that the proposed VCO have tuning range of 0.74 GHz from 58.09-to-58.83 GHz. The proposed VCO consumes 4 mW dc power from 1.2 V supply voltage.Item Admittance-Transforming Injection-Locked Frequency Divider and Low-Supply-Voltage Current Mode Logic Divider(2010-12-10) Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei HuangA injection-locked frequency divider (ILFD) with a 0.8-V current mode logic (CML) frequency divider are presented in this paper. These two frequency dividers are fabricated and integrated in 0.13-μm CMOS technology. The proposed ILFD adopts the admittance-transforming to widen the locking range. To achieve low-supply-voltage in CML frequency divider, the transconductance stage of CML divider is replaced by the inductance. Under 0 dBm injected power, the measured results show that the proposed ILFD have 22.8 % bandwidth from 40.5-to-50.9 GHz. Furthermore, the divider-by-four frequency divider composed of an ILFD and CML divider are measured with locking range from 42 to 45 GHz. The ILFD and CML divider consume 3.6 mW and 8 mW dc power from 0.6 V and 0.8 V supply voltage, respectively.Item An ultra low-power 24 GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process(2011-12-08) Yu-Hsuan Lin; Jeng-Han Tsai; Yen-Hung Kuo; Tian-Wei HuangA 24 GHz 29.8 mW Phase-lock-loop using 0.18 μm CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by -122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm2 without off-chip loop filter.Item A 24-GHz 3.8-dB NF Low-Noise Amplifier with Built-In Linearizer(2010-12-10) Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei HuangA K-band low-noise amplifier with built-in linearizer using 0.18-μm CMOS technology is presented in this paper. To achieve good linearity at high frequency, a distributed derivative superposition linearization technique is used. The measured results show that the improvement of IIP3 and IM3 are 5.3 dB and 10.6 dB at 24 GHz, respectively. The proposed LNA has a noise figure of 3.8 dB and a peak gain of 13.7 dB while consuming 18 mW dc power. To the best of our knowledge, this is the first LNA with a built-in linearizer above 20 GHz in CMOS.Item A 53-to-67 GHz low-power and wide-locking-range injection locked frequency divider with forward body bias(Wiley-Blackwell, 2011-06-01) Jeng-Han Tsai; Yu-Hang WongA 53–67 GHz wide locking range injection-locked frequency divider (ILFD) has been designed and fabricated using 0.13-μm CMOS process.By using forward body bias technique, the proposed ILFD demonstrates good performance of the wide locking range while maintaining low DC power consumption. Via a 0 dBm incident signal power, an input locking rage greater than 14 GHz (>23%) is achieved with 4 mW from supply voltage of 0.8 V. If the supply voltage further reduces to 0.6 V, the input locking rage is 6 GHz (10%) while consuming only 1.2 mW. Compared to previous reported works in high-speed CMOS FD, the presented ILFD achieves superior figure of merit (FOM). Without extra voltage control mechanisms to increase the locking range, this FD covers whole 57–64 GHz band is suitable for integration into a 60 GHz WPAN phase-locked loop systemItem A 0.6 V low-power 3.5 GHz CMOS low noise amplifier for WiMAX applications(Wiley-Blackwell, 2012-01-01) Jeng-Han Tsai; Yi-Jhang Lin; Hao-Chun YuIn this letter, a low-voltage and low-power 3.5-GHz low noise amplifier (LNA) is designed and fabricated using TSMC 0.18-lm MS/RF complementary metal-oxide-semiconductor field effect transistor (CMOS) technology. The complementary current-reused topology is utilized to achieve low dc power consumption while maintaining reasonable gain performance. Consuming 1.38 mW dc power from 0.6 V supply, the LNA achieves a small signal gain of 16.09 dB and a noise figure of 4.702 dB at 3.5 GHz. Compared with previously reported LNA, the MMIC has excellent FOM performance. VC 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:145–147, 2012; View this article online at wileyonlinelibrary.comItem Design of 1.2 V broadband, high data-rate CMOS MMW I/Q modulator and demodulator using modified Gilbert-cell mixer(IEEE Microwave Theory and Techniques Society, 2011-05-01) Jeng-Han TsaiIn this paper, low-voltage evolution and high-speed operation mixer design are presented for millimeter-wave (MMW) CMOS in-phase/quadrature (I/Q) modulator and demodulator. The modified Gilbert-cell mixer architecture, which eliminates the three-level transistors stacking in the conventional Gilbert-cell mixer, can operate at a reduced supply voltage while maintaining reasonable performance. In addition, IF transimpedance amplifier buffer and wideband RF design are introduced to increase the operation speed of the mixer for MMW gigabit wireless transmission link applications. Using a 0.13-μm CMOS process, the I/Q modulator and demodulator formed with the modified Gilbert-cell mixers are demonstrated at the MMW. Under 1.2-V standard supply voltage, the modulator and demodulator exhibit excellent conversion gain (CG) flatness of -3.5 ±1.5 dB and -3 ±1.5 dB from 41 to 69.5 GHz and 31 to 69 GHz, respectively. For 60-GHz wireless personal area network applications, π/4 differential quadrature phase-shift keying, 16 quadrature amplitude modulation, and binary phase-shift keying modulation signal tests are successfully performed through the direct-conversion system. The results show that the presented monolithic microwave integrated circuits can operate at low-voltage and low-power while providing good CG and high data rate, even up to multigigabit.Item Design and analysis of a 77.3% locking-range divide-by-4 frequency divider(IEEE Microwave Theory and Techniques Society, 2011-10-01) Yen-Hung Kuo; Jeng-Han Tsai; Hong-Yeh Chang; Tian-Wei HuangA cascoded frequency divider (FD) with division number of 4 and ultra-wide locking range is presented in this paper. The proposed FD consists of a divide-by-2 (D2) injection-locked frequency divider (ILFD) core and a D2 source-injection current mode logic (SICML) divider. After the cascoded integration of ILFD and SICML, the removal of transconductance and buffer stages can lower the dc power consumption and widen the locking range. The proposed FD is implemented in 0.13-μm CMOS technology and has a 77.3% frequency locking range from 13.5 to 30.5 GHz at injection power of 0 dBm while consuming 7.3-mW dc power. Compared to the previously reported ILFDs, the proposed circuit achieves the widest locking range without employing extra tuning mechanism.Item A 60-GHz CMOS power amplifier with built-in pre-distortion linearizer(Institute of Electrical and Electronics Engineers (IEEE), 2011-12-01) Jeng-Han Tsai; Chung-Han Wu; Hong-Yuan Yang; Tian-Wei HuangA built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power ampli- fier (PA) achieves a of 10.72 dBm and of 7.3 dBm from 1.2 V supply. After linearization, the has been doubled from 7.3 to 10.2 dBm and the operating PAE at consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.